1. Field of the Invention
This invention relates to a semiconductor memory device having a column redundancy system, and more particularly, to a semiconductor memory device for use as a video memory in which data are inputted and outputted serially and the data are converted into or from parallel data therein.
2. Description of the Prior Art
In general, a video memory such as a field memory has a memory cell array composed of DRAM type cells and is adapted to perform serial-parallel conversion and parallel-serial conversion during writing and reading, respectively, by means of a register, for inputting or outputting the serial data.
With such video memory, defects tend to be produced in memory cells because of the process, and a redundancy circuit is provided for rescuing the erroneous bits where the defect has occurred. In general, the column decoder is dispensed with a video memory because one-row data are written or read out collectively to or from the memory cell array. Therefore, if the defective memory cell column is exchanged to the redundancy circuit, since the addresses cannot be specified directly to the redundancy circuit, it becomes necessary to add various circuits.
FIG. 1 shows substantial portions of an example of the conventional memory device having a column redundant section. A read shift register 102 and a write shift register 103 are provided in a RAM section 101 having a memory cell array for data storage. In the read shift register 102, data are transmitted in parallel from the RAM section 101 and thence outputted serially. Data are inputted serially in the write shift register 103 and transferred in parallel to the RAM section 101. The RAM section 101 and a column redundant section 104 provided thereat are associated with a row decoder 105 to effect row section. The column redundant section 104 is adapted for rescuing column defects in RAM section 101 by row-by-row substitution and data to be stored intrinsically in the column defective portion are stored in the column redundant section 104. For such substitution, the video memory device is provided with a fuse ROM 110 for storing column-defective column data (column address), a write address comparator circuit 111W, a read addresses comparator circuit 111R, a write switching circuit 112W, a read switching circuit 112R, a write redundancy latch 113W and a read redundancy latch 113R. In the comparator circuits 111W, 111R, address data from address generators 106, 107 are compared with column-defective column data from fuse ROM 110 and, in case of coincidence of these data, the switching circuits 112W, 112R are switched to the latch side. As a result, data are written into the column redundant section 104, and data are read out from the column redundant section 104.
With the above described conventional video memory device, fuse ROM 110, comparator circuits 111R, 111W, switching circuits 112W, 112R and so forth, are necessitated for controlling the column redundant section 104, so that the corresponding area on the chip has been necessitated.
On the other hand, the read-out erroneous data are replaced by the redundant data by the switching circuit 112R with consumption of excess time.